1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (“LCD”) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along a certain direction. An alignment direction of the liquid crystal molecules depends on the intensity and the direction of an electric field applied to the liquid crystal molecules. Light passes through the LCD device along the alignment direction of the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment direction of the liquid crystal molecules changes and images are displayed.
Generally, an LCD device includes two substrates, which are spaced apart facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face each other. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. Normally, the direction of the electric field is perpendicular to the substrates. Active matrix liquid crystal display (“AMLCD”) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display images moving fast.
The LCD device will be described hereinafter with reference to accompanying drawings. FIG. 1 is a schematic perspective view of an LCD device according to the related art. In FIG. 1, an LCD device 51 includes a first substrate 5 and a second substrate 10 spaced apart from each other. A liquid crystal layer (not shown) is interposed between the first and second substrates 5 and 10. A black matrix 6 and a color filter layer (7a, 7b, and 7c) is formed on an inner surface of the first substrate 5, which faces the second substrate 10. A common electrode 9 is formed on the color filter layer (7a, 7b, and 7c.). The color filter layer (7a, 7b, and 7c) includes color filters of red, green and blue 7a, 7b, and 7c. 
Gate lines 14 and data lines 26 are formed on an inner surface of the second substrate 10, which faces the first substrate 5. The gate lines 14 and the data lines 26 cross each other to define pixel regions P. A thin film transistor T is formed at each crossing point of the gate and data lines 14 and 26. A pixel electrode 32 is formed in each pixel region P and is connected to the thin film transistor T. The pixel electrode 32 is formed of a transparent conductive material that transmits light relatively well, such as indium tin oxide (ITO).
The first substrate 5, which includes the black matrix 6, the color filter layer, and the common electrode 9, may be referred to as a color filter substrate. The second substrate 10, which includes the gate lines 14, the data lines 26, the thin film transistors T, and the pixel electrodes 32, may be referred to as an array substrate.
The array substrate may be manufactured through five or six mask processes. An example of manufacturing an array substrate through five mask processes is as follows. Gate lines, gate electrode and gate pads are formed on a substrate through a first mask process. Active layers and ohmic contact layers are formed through a second mask process. Data lines, source electrodes, drain electrodes and data pads are formed through a third mask process. A passivation layer is formed substantially on an entire surface of the substrate, and contact holes exposing the drain electrodes are formed in the passivation layer through a fourth mask process. Pixel electrodes, which are connected to the drain electrodes through the contact holes, are formed through a fifth mask process.
The mask process includes many steps of coating a thin film with photoresist, exposing the photoresist to light, developing the photoresist, etching the thin film, and removing the photoresist. As the number of mask processes increases, manufacturing costs and time increase correspondingly. In addition, the probability that problems may occur also increases, resulting in a decrease in the productivity.
To solve the problems, four mask processes for manufacturing the array substrate have been proposed. FIG. 2 is a plan view of an array substrate for an LCD device manufactured through four mask processes according to the related art. In FIG. 2, gate lines 62 are formed on a substrate 60, and data lines 98 cross the gate lines 62 to define pixel regions P. A gate pad 66 is formed at one end of each gate line 62, and a data pad 99 is formed at one end of each data line 98. A gate pad electrode GP is formed on the gate pad 66 and contacts the gate pad 66. A data pad electrode DP is formed on the data pad 99 and contacts the data pad 99. A thin film transistor T is formed at each crossing point of the gate and data lines 62 and 98. The thin film transistor T includes a gate electrode 64, a first semiconductor layer 90a, and source and drain electrodes 94 and 96. The gate electrode 64 is connected to the gate line 62. The first semiconductor layer 90a is disposed over the gate electrode 64. The source and drain electrodes 94 and 96 are formed on the first semiconductor layer 90a and are spaced apart from each other. The source electrode 94 is connected to the data line 98. A transparent pixel electrode PXL is formed in each pixel region P. The pixel electrode PXL is connected to the drain electrode 96.
A metallic layer 86 is formed over a part of each gate line 62 and is connected to the pixel electrode PXL. The metallic layer 86 has an island shape. The gate line 62 and the metallic layer 86 form a storage capacitor Cst with a gate insulating layer (not shown) interposed therebetween. The gate line 62 functions as a first electrode, the metallic layer 86 functions as a second electrode, and the gate insulating layer functions as a dielectric substance. A second semiconductor layer 90b is formed under the data line 98. A third semiconductor layer 90c is formed under the metallic layer 86. The second semiconductor layer 90b extends from the first semiconductor layer 90a. 
In the array substrate manufactured through four mask processes, intrinsic amorphous silicon layers are exposed at edges of the source and drain electrodes 94 and 96 and the data line 98. When the intrinsic amorphous silicon layers are exposed to light, photo-leakage currents are generated. The photo-leakage current couples with the pixel electrode PXL and causes wavy noise in the image displayed.
FIGS. 3A and 3B are cross-sectional views along the line II-II and the line V-V of FIG. 2, respectively, of an array substrate according to the related art. In FIGS. 3A and 3B, when the array substrate is manufactured through a four mask process, a first semiconductor layer 90a is formed under both source and drain electrodes 94 and 96, and a second semiconductor layer 90b is formed under the data line 98. Each of the first and second semiconductor layers 90a and 90b includes an intrinsic amorphous silicon layer (a-Si:H) and an impurity-doped amorphous silicon layer (for example, n+a-Si:H). The intrinsic amorphous silicon layer of the first semiconductor layer 90a is referred to as an active layer 92a, and the impurity-doped amorphous silicon layer of the first semiconductor layer 90a is referred to as an ohmic contact layer 92b. The intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b is exposed at both sides of the data line 98, and the active layer 92a is exposed at sides of the source and drain electrodes 94 and 96. That is, the intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b has a larger area than the data line 98, and electrical conductivity increases in the intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b. The intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b is exposed to a light source (not shown), and photo-leakage currents are caused in the intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b. The intrinsic amorphous silicon layer 70 is repeatedly activated and inactivated according to On/Off states of the light source, and the photo-leakage currents changes accordingly. The photo-leakage currents affect a parasitic capacitance between the data line 98 and the pixel electrode PXL, and the parasitic capacitance varies according to the change of the photo-leakage currents. Signals of the pixel electrode PXL also change. Therefore, the liquid crystal molecules over the pixel electrode PXL are distorted, resulting in wavy lines on the displayed image. Moreover, the photo-leakage currents in the active layer 92a cause additional problems in the operation of the thin film transistor T.
Meanwhile, the intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b has a protruded part with a width of about 1.7 μm beyond each side of the data line 98. Generally, the data line 98 and the pixel electrode PXL have a separation of about 4.75 μm therebetween, considering the alignment margin. However, the distance “d” between the data line 98 and the pixel electrode PXL should be about 6.45 μm because of the protruded part. The pixel electrode PXL becomes more distant from the data line 98 by the width of the protruded part of the intrinsic amorphous silicon layer 70. A black matrix BM covering an area between the data line 98 and the pixel electrode PXL has a width W1. The aperture area decreases by W1 due to the black matrix BM. As stated above, the formation and structure of the second semiconductor layer 90 under the data line 98 are due to four mask processes. Hereinafter, four mask processes will be described with reference to accompanying drawings.
FIGS. 4A to 4G, FIGS. 5A to 5G and FIGS. 6A to 6G are cross-sectional views of an array substrate showing processes of manufacturing the same according to the related art. FIGS. 4A to 4G correspond to cross-sectional views along the line II-II of FIG. 2, FIGS. 5A to 5G correspond to cross-sectional views along the line III-III of FIG. 2, and FIGS. 6A to 6G correspond to cross-sectional views along the line IV-IV of FIG. 2.
FIG. 4A, FIG. 5A, and FIG. 6A show the array substrate in a first mask process. In FIG. 4A, FIG. 5A, and FIG. 6A, a switching region S, a pixel region P, a gate region G, a data region D, and a storage region C are defined on a substrate 60. The pixel region P includes the switching region S. The gate region G includes the storage region C.
A gate line 62, a gate pad 66, and a gate electrode 64 are formed on the substrate 60 including the regions S, P, G, D and C. The gate pad 66 is formed at one end of the gate line 62. The gate electrode 64 is connected to the gate line 62 and is disposed in the switching region S. The gate line 62, the gate pad 66 and the gate electrode 64 are formed by depositing a conductive metal consisting of one or more material from a conductive metallic group including aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). The gate line 62, the gate pad 66 and the gate electrode 64 may be formed by a single layer of the above-mentioned metallic material or may be a double layer of aluminum (Al)/chromium (Cr) or aluminum (Al)/molybdenum (Mo).
FIGS. 4B to 4E, FIGS. 5B to 5E and FIGS. 6B to 6E show a second mask process. In FIG. 4B, FIG. 5B and FIG. 6B, a gate insulating layer 68, an intrinsic amorphous silicon layer (a-Si:H) 70, an impurity-doped amorphous silicon layer (n+ or p+a-Si:H) 72, and a conductive metallic layer 74 are formed substantially on an entire surface of the substrate 70 including the gate line 62, the gate pad 66 and the gate electrode 64.
The gate insulating layer 68 is formed of an inorganic insulating material including silicon nitride (SiNX) and silicon oxide (SiO2) or an organic insulating material including benzocyclobutene (BCB) and acrylic resin. The conductive metallic layer 74 is formed of a conductive metal consisting of one or more material from a conductive metallic group including aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo).
A photoresist layer 76 is formed by coating an entire surface of the substrate 60 including the conductive metallic layer 74 with photoresist. A mask M is disposed over the photoresist layer 76. The mask M includes a light-transmitting portion B1, a light-blocking portion B2, and a light-half transmitting portion B3. The light-transmitting portion B1 transmits substantially all light. The photoresist layer 76 below the light-transmitting portion B1 is entirely exposed to light to thereby chemically change. The light-blocking portion B2 completely blocks the light. The light-half transmitting portion B3 includes slits or a half transparent layer to decrease the intensity of light or transmittance of the light. Thus, the photoresist layer is partially exposed to light therethrough.
The light-half transmitting portion B3 is disposed over the gate electrode 64 in the switching region S. The light-blocking portion B2 is disposed in the storage region C, in the switching region S and in the data region D. In the switching region S, the light-blocking portion B2 is disposed at both sides of the light-half transmitting portion B3. The light-transmitting portion B1 is disposed in other regions. The photoresist layer 76 is exposed to light through the mask M and then is developed.
In FIG. 4C, FIG. 5C and FIG. 6C, first, second and third photoresist patterns 78a, 78b and 78c are formed in the switching region S, the data region D, and the storage region C. The conductive metallic layer 74 is partially exposed. Next, the exposed conductive metallic layer 74, the impurity-doped amorphous silicon layer 72 thereunder, and the intrinsic amorphous silicon layer 70 are removed. The conductive metallic layer 74 may be removed simultaneously with the under layers 72 and 70. Alternatively, the conductive metallic layer 74 may be wet-etched. Then, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 may be dry-etched.
In FIG. 4D, FIG. 5D and FIG. 6D, a first metallic pattern 80, a second metallic pattern 82, and a third metallic pattern 86 are formed under the first, second, and third photoresist patterns 78a, 78b and 78c, respectively. Although not shown, the second metallic pattern 82 extends from the first metallic pattern 80 along a side of the pixel region P. The third metallic pattern 86 corresponds to the storage region C and has an island shape. A first semiconductor pattern 90a, a second semiconductor pattern 90b, and a third semiconductor pattern 90c are formed under the first metallic pattern 80, the second metallic pattern 82 and the third metallic pattern 86, respectively. Each of the first, second, and third semiconductor patterns 90a, 90b, and 90c includes the intrinsic amorphous silicon layer 70 and the impurity-doped amorphous silicon layer 72.
Next, an ashing process is performed to remove a part of the first photoresist pattern 78a corresponding to the gate electrode 64, and the first metallic pattern 80 is exposed. At this time, other parts of the first photoresist pattern 78a, the second photoresist pattern 78b, and the third photoresist pattern 78c are partially removed. The thicknesses of the first, second, and third photoresist patterns 78a, 78b and 78c are decreased. The first, second, and third metallic patterns 80, 82 and 86 are partially exposed at peripheries of the first, second and third photoresist patterns 78a, 78b and 78c. 
In FIG. 4E, FIG. 5E and FIG. 6E, the exposed first metallic pattern 80 and the impurity-doped amorphous silicon layer 72 of the first semiconductor layer 90a of FIG. 4D are removed. A source electrode 94, a drain electrode 96, and an ohmic contact layer 92b are formed. The intrinsic amorphous silicon layer of the first semiconductor layer 90a functions as an active layer 92a. When the impurity-doped amorphous silicon layer 72 of the first semiconductor layer 90a in FIG. 4D is removed, the intrinsic amorphous silicon layer, i.e., the active layer 92a, is over-etched so that particles may not remain on the surface of the active layer 92a. 
The second metallic pattern 82 of FIG. 6D, which contacts the source electrode 94, becomes a data line 98, and one end of the data line 98 becomes a data pad 99. The third metallic pattern 86 of an island shape and the gate line 62 in the storage region C function as electrodes for a capacitor. The gate line 62 functions as a first electrode, and the third metallic pattern 86 functions as a second electrode. The gate line 62, the gate insulating layer 68, the third semiconductor pattern 90c, and the third metallic pattern 86 constitute a storage capacitor Cst. Next, the photoresist patterns 78a, 78b and 78c are removed.
FIG. 4F, FIG. 5F and FIG. 6F show a third mask process. In FIG. 4F, FIG. 5F and FIG. 6F, a passivation layer PAS is formed substantially on an entire surface of the substrate 60 including the source and drain electrodes 94 and 96, the data line 98 including the data pad 99, and the storage capacitor Cst. The passivation layer PAS may be formed by depositing an inorganic insulating material selected from an inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO2). The passivation layer PAS may also be formed by coating the substrate 60 with an organic insulating material selected from an organic insulating material group including benzocyclobutene (BCB) and acrylic resin.
Subsequently, the passivation layer PAS is patterned to form a drain contact hole CH1, a storage contact hole CH2, a gate pad contact hole CH3, and a data pad contact hole CH4. The drain contact hole CH1 partially exposes the drain electrode 96. The storage contact hole CH2 exposes the third metallic pattern 86. The gate pad contact hole CH3 partially exposes the gate pad 66. The data pad contact hole CH4 partially exposes the data pad 99.
FIG. 4G, FIG. 5G and FIG. 6G show a fourth mask process. In FIG. 4G, FIG. 5G and FIG. 6G, a pixel electrode PXL, a gate pad electrode GP, and a data pad electrode DP are formed on the substrate 60 including the passivation layer PAS by depositing a conductive metal selected from a transparent conductive metallic group including indium tin oxide (ITO) and indium zinc oxide (IZO), and then patterning it. The pixel electrode PXL contacts the drain electrode 96 and the third metallic pattern 86. The gate pad electrode GP contacts the gate pad 66. The data pad electrode DP contacts the data pad 99.
The array substrate for a liquid crystal display device may be manufactured through the above-mentioned four mask processes. The manufacturing costs and time can be reduced. The probability that problems may occur also decreases.
However, in the array substrate manufactured through four mask processes, the semiconductor layer is exposed at both sides of the data line. The exposed semiconductor layer is affected by light and causes wavy noise on images that are displayed. In addition, the aperture ratio decreases due to the semiconductor layer.